1. Field of the Invention
Generally, the invention relates to error correction systems, and more particularly to a composite encoder/syndrome generator for generating both check symbols and error syndromes.
2. Discussion of the Related Art
In order to adjust error correction capability when using a Reed-Solomon (RS) code, it is necessary that this capability be adjustable in both the encoder and decoder. FIG. 1 illustrates an algebraic error correction system embodying a prior art RS encoder/decoder that includes a composite encoder/syndrome generator circuit 30. The circuit 30 generates check symbols that are appended to uncorrupted input data supplied via bus 31 and transmitted via bus 32 to a channel 45 that is subject to noise. The composite encoder/syndrome generator circuit 30 also computes error syndromes from potentially noise-corrupted data received via bus 33 from the channel 45.
As illustrated, the circuit 30 comprises a plurality of fixed multipliers 51 with respective preselected multiplier values (i.e., tap weights) of a0, a1, a2 . . . a2t-1, latches 34a, 34b, 34c . . . 34n, and adders 35a, 35b, 35c . . . 35n, where “n” is an integer greater than one. Each multiplier 51, latch 34, and associated adder 35 constitutes a multiplier module 50. Each multiplier module 50 is associated with an adder 36 (i.e., adders 36a, 36b . . . 36n−1), an AND gate 37 (i.e., AND gates 37a, 37b, 37c . . . 37n), and an AND gate (i.e., AND gates 38a, 38b, 38c . . . 38n). The AND gates 38 each have one input that is constantly on (i.e., having a logical “1” input). The error correction system also includes multiplexors (MUXs) 39A, 39B, 39C, a controller 40, and a programmable ECC power selection circuit 41.
To correct “t” symbols in error, 2t check symbols and 2t error syndromes are generated. The number of check symbols that are generated depends upon the programmed value of “r” which determines the number of multiplier modules 50 that are activated in the circuit 30. For example, if r=2, all control lines to the left of 2t−2 (i.e., r>2t−2 and r>2t−1) are deactivated. Accordingly, only the rightmost multiplier modules 50 with the fixed multipliers (a2t-2, a2t-1) receive incoming data.
In operation, to encode uncorrupted incoming data, a controller 40 (via signal line 42) causes the switch 43 to be biased to its upper position. The controller 40, via signal line 44, also conditions the MUX 39A to transmit uncorrupted incoming data from bus 31 via the switch 43 to bus 32. From bus 32, the data is transferred to a MUX 39B. The MUX 39B causes the data to be transferred to the channel 45. Data from the bus 32 is also concurrently transferred to the adders 35, latches 34, and multipliers 51 of the enabled multiplier modules 50 for computing check symbols, the values of which are stored in their respective latches 34.
When transmission of data via the bus 32 to the channel 45 is complete, the controller 40 transfers a control signal to the signal line 42, which causes the switch 43 to be pulled to its lower position thereby disconnecting the bus 32 from the uncorrupted data. Meanwhile, the programmable ECC power selection circuit 41 is conditioned by a preselected value for r from 0 to 2t−1 in line 46 to provide corresponding outputs via corresponding control lines labeled r>1 . . . r>2t−1. The signal line 42 transfers a control signal to all AND gates 38a through 38n. Again, if r=2, only the two rightmost AND gates 38n−1 and 38n are activated to feed the check bytes stored in the latches 34n−1 through 34n of the respective multiplier modules 50 sequentially starting from the rightmost multiplier module 50 under control of a clock (not shown) and as permitted by the AND gate 38n. The MUX 39C is conditioned by the signal in the control line 44 to cause these check bytes to be transmitted to the channel 45 and appended to the uncorrupted input data previously transmitted via the switch 43 in upper position. Note that the AND 38n is necessary to isolate latch 34n from the MUX 39C unless line 42 is on.
For decoding, the MUXs 39A and 39B are conditioned by the control signal via the control line 44 from the controller 40 to pass the data to be decoded from the bus 33 via the switch 43 in upper position and then via the bus 32 to the buffer 47. Also during encoding, the data is transferred to the various multiplier modules 50 to generate error syndromes, which are stored in the respective latches 34a . . . 34n. 
After the data to be decoded has been transmitted to the buffer 47, the controller 40 activates the control line 42 to cause the error syndromes stored in the latches 34c . . . 38n to be shifted out through the MUX 39C to the decoder 48. With the selection circuit 41 conditioned by the selected value of r to deactivate all of the control lines to the left of 2t−2, only the multiplier modules 50 to the right of r>2t−2 are activated.
While the encoder/syndrome generator circuit 30 provides an effective means for Reed Solomon encoding and decoding within a single device, a problem exists in the implementation of the circuit 30. More specifically, the successive feeding of one multiplier module 50 to another has a multiplicative effect on the logical delay. For example, each AND gate 37 has some logical time delay 37delay while each adder 36 also has some logical time delay 36delay. If n multiplier modules 50 are selected, the associated logical delay becomes n (37delay+36delay). This logical delay becomes increasingly intolerable as the level of error correction encoding/decoding increases.